Introduction to NAND Flash
NAND Flash memory stores data in an array of memory cells made from floating-gate transistors. Insulated by an oxide layer are two gates, the Control Gate (CG, top) and the Floating Gate (FG, bottom). Electrons flow freely between the CG and the Channel (see diagram to the right) when a voltage is applied to either entity, attracted in the direction to which the voltage is applied. To program a cell, a voltage is applied at the CG, attracting electrons upwards. The floating gate, which is electrically isolated by an insulating layer, traps electrons as they pass through on their way to the CG. They can remain there for up to years at a time under normal operating conditions. To erase a cell, a voltage is applied at the opposite side (the Channel) while the CG is grounded, attracting electrons away from the floating gate and into the Channel.
To check the status of a cell, a high voltage is applied to the CG. If the floating gate holds a charge (electrons are trapped there), the threshold voltage of the cell is altered, affecting the signal emanating from the CG as it travels through to the Channel. The precise amount of current required to complete the circuit determines the state of the cell. All of this electrical activity effectively wears out the physical structure of the cell over time. Thus, each cell has a finite lifetime, measured in terms of Program/Erase (P/E) cycles and affected by both process geometry (manufacturing technique) and the number of bits stored in each cell. The complexity of NAND storage necessitates some extra management processes, including bad block management, wear leveling, garbage collection (GC), and Error Correcting Code (ECC), all of which is managed by the device firmware through the SSD controller.
SLC vs. MLC vs. TLC
NAND technology has been naturally progressing with the needs and expertise of the industry. In the simplest terms, the data stored in NAND flash is represented by electrical charges that are stored in each NAND cell. The difference between Single-Level Cell (SLC) and Multi-Level Cell (MLC) NAND is in how many bits each NAND cell can store at one time. SLC NAND stores only 1 bit of data per cell. As their names imply, 2-bit MLC NAND stores 2 bits of data per cell and 3-bit MLC NAND stores 3 bits of data per cell. 3-bit MLC is referred to as Triple Level Cell (TLC) Demonstrated in diagram 1.0 below
Advantages of MLC and TLC NAND
The more bits a cell stores at one time, the more capacity that fits in one place, thus reducing manufacturing costs and increasing NAND manufacturing capacity – a phenomenon called “bit growth.” This phenomenon has allowed NAND technology to penetrate a continually greater number of usage applications at increasingly higher capacities over the years. NAND technology’s first home was in external storage devices (e.g. USB memory devices) at very modest capacities. As the technology matured, NAND found applications in a host of digital devices, including digital cameras, MP3 players, and mobile phones. Having proven itself a strong and durable performer, the technology made its way into consumer and finally enterprise solid state storage devices (SSDs). NAND’s rise in popularity and usefulness was directly a result of the advances in semiconductor technology that allowed engineers to squeeze more bits into each cell. Capacities ballooned from megabytes (MBs) to gigabytes (GBs) as manufacturers were able to produce the same NAND bit capacity with less capital investment. A self-reinforcing cycle of increasing demand and decreasing pricing helped manufacturers to continue to meet industry needs without increasing supply costs – benefiting both consumers and device makers.
Limitations of MLC and TLC NAND
Of course, adding more bits to each cell makes it more difficult to distinguish between states (refer to diagram 1.0), reducing reliability, endurance, and performance. Indeed, determining whether a container is either full or empty (SLC) is much simpler than determining whether it is one quarter full, one half full, three-quarters full, or entirely full (MLC). This is why it can take up to 4 times as long to write and up to 2.5 times as long to read 3-bit MLC NAND than its SLC predecessor. Another side effect of storing more bits per cell is an increase in the rate at which the NAND cells degrade. The state of a NAND cell is determined by the number of electrons present on the floating gate. The Oxide layers that trap electrons on the floating gate wear out with every program and erase operation. As they wear out, electrons become trapped, which affects the overall electrical properties of the cell and, consequentially, subsequent program and erase operations. With the oxide weakened, charges sometimes leak from the floating gate. While this is not a huge problem with SLC NAND because there are only two states to distinguish between, it can be a huge problem for 3-bit MLC NAND because there are 8 states to distinguish and very little room for differentiation – just a few electrons can make the difference between one state or another. Compounding matters is the fact that the oxide layer gets smaller with each advance in process geometry – as we shrink the size of the cell, the oxide becomes thinner. A thinner oxide layer will wear out faster, meaning the cell will have a lower lifespan.
Bridging the Gap with Pseudo SLC
Pseudo SLC (pSLC) is a hybrid of 2 Bit per Cell MLC using clever firmware to emulate the storage states of SLC. The results are increased endurance on MLC (20-30K Program / Erase Cycles) but only at a fraction of the cost when compared to SLC. For industrial computing this offers a great middle ground when cost and reliability are of equal importance. However you will need to consider because the NAND is MLC based it will follow the same rate of technology evolution.