New Die package extends ATP 3D TLC eMMC endurance

Published 22 February 2022

The ATP industrial e.MMC is an advanced storage solution that integrates NAND flash memory, a sophisticated flash controller, and a fast MultiMedia Card (MMC) interface in the same package. By incorporating these components in an integrated package, ATP e.MMC manages all background operations internally, freeing the host from handling low-level flash operations for faster and more efficient processing. 

Smaller than a typical postage stamp, ATP e.MMC comes in a 153-ball fine pitch ball grid array (FBGA package). The tiny footprint makes it perfectly suitable for embedded systems with space constraints but require rugged endurance, reliability and durability in harsh environments. 

ATP e.MMC is built to meet the tough demands of industrial applications. As a soldered-down solution, it is secure against constant vibrations. Its industrial temperature rating means that severe scenarios from freezing cold -40°C to blistering hot 105°C will not cause adverse impact on the device or the data in it. 

ATP’s latest line of e.MMC devices built on 3D triple level cell (TLC) NAND use a new die package to deliver long-life performance, optimized power consumption and customizable configuration options.

•    E750Pi/Pc Series e.MMC offerings are built with 3D TLC NAND flash but are configured as pseudo SLC (pSLC) to offer endurance on par with SLC NAND
•    E650Si/Sc Series in native TLC has near-MLC endurance

The E750Pi and E650Si Series are industrial temperature-operable (-40°C to 85°C), making them ideal for deployment in scenarios with extreme thermal challenges and harsh environments, while E750Pc and E650Sc support -25°C to 85°C operating temperatures for applications with non-critical thermal requirements.

Data Integrity Features

The ATP E750Pi/Pc and E650Si/Sc Series e.MMC feature the following technologies to ensure high levels of data integrity:

  • AutoRefresh Technology improves the data integrity of read-only areas by monitoring the error bit level and read counts in every read operation.
  • Dynamic Data Refresh Technology reduces the risks of read disturb and sustains data integrity in seldom-accessed areas.
  • SRAM Soft Error Detector and Recovery mechanism maximizes data integrity by monitoring soft errors, which cannot be detected nor solved by ECC engines and can therefore significantly jeopardize data accuracy.
  • Low-Density Parity-Check Error Correcting Code (LDPC ECC) provides powerful error correction to significantly improve data transfer reliability.